The tutorial will provide first, a brief insight of innovative techniques for power estimation at the RTL. Then, it will be entirely devoted to the practical use of the BullDAST PowerChecker environment on actual designs provided by the partner comapanies Accent and STMicroelectronics.

The attendees will be given complete design examples and will be guided into the PowerChecker tool flow. First, power consumption of the considered designs will be estimated by PCE, the RTL power estimation engine available within PowerChecker.
Next, based on the results of the estimation step, the attendees will invoke the optmization engines available in PowerChecker (i.e., MemArt, CoolBus, CGCap and LPClock).
More specifically, MemArt performs automatic partitioning of monolithic memory components; CoolBus allows the exploration of different encoding schemes, suggests the power optimal one and updates the RTL netlist accordingly; CGCap optimizes power consumption of control and steering logic by detecting idle conditions that cannot be captured by simple topological analysis; LPClock automatically generates the clock tree structure for a RTL netlist based on both switching activity and placement information by providing, as output, constraints for the clock synthesis tool.

This hands-on tutorial will demonstrate to the trainees how opportunities for power optmization do exist while shortening the design time and enhancing the design productivity.